PIC16C71X
Applicable Devices 710 71 711 715
FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
200
7*
—
—
ns
VDD = 5V, -40˚C to +85˚C
VDD = 5V, -40˚C to +85˚C
Twdt
Watchdog Timer Time-out Period
18
33*
ms
(No Prescaler)
32
33
34
Tost
Oscillation Start-up Timer Period
—
28*
—
1024 TOSC
—
—
ms
ns
TOSC = OSC1 period
Tpwrt Power-up Timer Period
I/O High Impedance from MCLR
Low
72
—
132*
100
VDD = 5V, -40˚C to +85˚C
TIOZ
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated.These parameters are for design guidance only
and are not tested.
1997 Microchip Technology Inc.
DS30272A-page 143
MICROCHIP [ MICROCHIP ]
