PIC16C71X
Applicable Devices 710 71 711 715
FIGURE 15-6: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 15-7: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
PIC16C71
PIC16LC71
PIC16C71
PIC16LC71
130
TAD
A/D clock period
2.0
2.0
2.0
3.0
—
—
—
—
—
µs
TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC Mode
µs A/D RC Mode
TAD
4.0
6.0
9.5
6.0
9.0
—
131
132
TCNV Conversion time
(not including S/H time) (Note 1)
TACQ Acquisition time
Note 2
5*
20
—
—
—
µs
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than
1 LSb (i.e., 19.5 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134
135
TGO
Q4 to A/D clock start
—
Tosc/2§
—
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
TSWC Switching from convert → sample time
1.5§
—
TAD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
These specifications ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for min conditions.
DS30272A-page 146
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
