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PIC16F628-04/SS 参数 Datasheet PDF下载

PIC16F628-04/SS图片预览
型号: PIC16F628-04/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
TABLE 4-2:  
SPECIAL FUNCTION REGISTERS SUMMARY BANK1  
Value on  
all other  
resets(1)  
Value on  
POR  
Reset  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Bank 1  
80h  
INDF  
OPTION  
Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx  
ister)  
xxxx xxxx  
81h  
82h  
83h  
84h  
85h  
86h  
87h  
88h  
89h  
8Ah  
8Bh  
8Ch  
8Dh  
8Eh  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
96h  
97h  
98h  
99h  
9Ah  
9Bh  
9Ch  
9Dh  
9Eh  
9Fh  
RBPU  
Program Counter’s (PC) Least Significant Byte  
IRP RP1 RP0 TO  
Indirect data memory address pointer  
INTEDG  
T0CS  
T0SE  
PSA  
PD  
PS2  
Z
PS1  
DC  
PS0  
C
1111 1111  
0000 0000  
0001 1xxx  
xxxx xxxx  
11-1 1111  
1111 1111  
1111 1111  
0000 0000  
000q quuu  
uuuu uuuu  
11-1 1111  
1111 1111  
PCL  
STATUS  
FSR  
TRISA  
TRISA7 TRISA6  
TRISA4 TRISA3 TRISA2  
TRISA1  
TRISB1  
TRISA0  
TRISB0  
TRISB  
TRISB7 TRISB6  
TRISB5 TRISB4 TRISB3 TRISB2  
Unimplemented  
Unimplemented  
Unimplemented  
PCLATH  
Write buffer for upper 5 bits of program counter  
---0 0000  
0000 000x  
---0 0000  
0000 000u  
0000 -000  
INTCON  
GIE  
EEIE  
PEIE  
CMIE  
T0IE  
INTE  
TXIE  
RBIE  
T0IF  
INTF  
RBIF  
PIE1  
RCIE  
CCP1IE  
TMR2IE TMR1IE 0000 -000  
Unimplemented  
PCON  
OSCF  
POR  
BOD  
---- 1-0x  
---- 1-uq  
Unimplemented  
Unimplemented  
Unimplemented  
PR2  
Timer2 Period Register  
11111111  
11111111  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
TXSTA  
CSRC  
TX9  
TXEN  
SYNC  
BRGH  
TRMT  
TX9D  
0000 -010  
0000 0000  
xxxx xxxx  
xxxx xxxx  
---- x000  
--------  
0000 -010  
0000 0000  
uuuu uuuu  
uuuu uuuu  
---- q000  
--------  
SPBRG  
Baud Rate Generator Register  
EEPROM data register  
EEDATA  
EEADR  
EEPROM address register  
EECON1  
WRERR WREN  
WR  
RD  
EECON2  
EEPROM control register 2 (not a physical register)  
Unimplemented  
VRCON  
VREN VROE VRR VR3  
VR2  
VR1  
VR0  
000- 0000  
000- 0000  
Legend: : — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,  
shaded = unimplemented  
Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during  
normal operation.  
DS40300B-page 16  
Preliminary  
1999 Microchip Technology Inc.  
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