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PIC16F628-04/SS 参数 Datasheet PDF下载

PIC16F628-04/SS图片预览
型号: PIC16F628-04/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
4.2.2.1  
STATUS REGISTER  
It is recommended, therefore, that only BCF, BSF,  
SWAPF and MOVWF instructions are used to alter the  
STATUS register because these instructions do not  
affect any status bit. For other instructions, not affecting  
any status bits, see the “Instruction Set Summary”.  
The STATUS register, shown in Register 4-1, contains  
the arithmetic status of the ALU, the RESET status and  
the bank select bits for data memory (SRAM).  
The STATUS register can be the destination for any  
instruction, like any other register. If the STATUS  
register is the destination for an instruction that affects  
the Z, DC or C bits, then the write to these three bits is  
disabled. These bits are set or cleared according to the  
device logic. Furthermore, the TO and PD bits are not  
writable. Therefore, the result of an instruction with the  
STATUS register as destination may be different than  
intended.  
Note 1: The C and DC bits operate as a Borrow  
and Digit Borrow out bit, respectively, in  
subtraction. See the SUBLW and SUBWF  
instructions for examples.  
For example, CLRF STATUSwill clear the upper-three  
bits and set the Z bit. This leaves the status register as  
000uu1uu(where u= unchanged).  
REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)  
R/W-0  
IRP  
R/W-0  
RP1  
R/W-0  
RP0  
R-1  
TO  
R-1  
PD  
R/W-x  
Z
R/W-x  
DC  
R/W-x  
C
R = Readable bit  
W = Writable bit  
bit7  
bit0  
U = Unimplemented bit,  
read as ’0’  
-n = Value at POR reset  
-x = Unknown at POR reset  
bit 7:  
IRP: Register Bank Select bit (used for indirect addressing)  
1= Bank 2, 3 (100h - 1FFh)  
0= Bank 0, 1 (00h - FFh)  
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)  
11= Bank 3 (180h - 1FFh)  
10= Bank 2 (100h - 17Fh)  
01= Bank 1 (80h - FFh)  
00= Bank 0 (00h - 7Fh)  
bit 4:  
bit 3:  
bit 2:  
bit 1:  
bit 0:  
TO: Time-out bit  
1= After power-up, CLRWDTinstruction, or SLEEPinstruction  
0= A WDT time-out occurred  
PD: Power-down bit  
1= After power-up or by the CLRWDTinstruction  
0= By execution of the SLEEPinstruction  
Z: Zero bit  
1= The result of an arithmetic or logic operation is zero  
0= The result of an arithmetic or logic operation is not zero  
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)  
1= A carry-out from the 4th low order bit of the result occurred  
0= No carry-out from the 4th low order bit of the result  
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)  
1= A carry-out from the most significant bit of the result occurred  
0= No carry-out from the most significant bit of the result occurred  
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the  
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of  
the source register.  
1999 Microchip Technology Inc.  
Preliminary  
DS40300B-page 19  
 
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