PIC16F62X
FIGURE 3-1:
BLOCK DIAGRAM
13
8
Data Bus
RAM
Program Counter
FLASH
Program
Memory
Data EEPROM
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
PORTA
RAM Addr (1)
9
Addr MUX
RA0/AN0
RA1/AN1
Instruction reg
Indirect
Addr
7
Direct Addr
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/THV
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
8
FSR reg
STATUS reg
8
3
PORTB
MUX
Power-up
Timer
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
RB6/T1OSO/T1CKI
RB7/T1OSI
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Detect
Low-Voltage
Programming
MCLR VDD, VSS
Timer0
CCP1
Timer1
Timer2
Comparator
USART
VREF
Memory
Device
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627
1024 x 14
2048 x 14
1024 x 14
2048 x 14
224 x 8
224 x 8
224 x 8
224 x 8
128 x 8
128 x 8
128 x 8
128 x 8
PIC16F628
PIC16LF627
PIC16LF628
Note 1: Higher order bits are from the STATUS register.
DS40300B-page 10
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
