PIC16C745/765
13.2.4 EXTERNAL CLOCK IN
13.2.5 E4 MODE
In EC mode, users may directly drive the PIC16C745/
765 provided that this external clock source meets the
AC/DC timing requirements listed in Section 17.4.
Figure 13-2 below shows how an external clock circuit
should be configured.
In E4 mode, a PLL module is switched on in-line with
the clock provided to OSC1. The output of the PLL
drives FINT.
Note: CLKOUT is the same frequency as OSC1 if
in E4 mode, otherwise CLKOUT = OSC1/4.
FIGURE 13-2: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
ext. system
OSC1
PIC16C745/765
CLKOUT
OSC2/CLKOUT
FIGURE 13-3: OSCILLATOR/PLL CLOCK CONTROL
6 MHz
EC
E4
OSC2
HS
H4
EC
E4
HS
H4
Q Clock
24 MHz
To Circuits
Generator
FINT
OSC1
4x PLL
A simplified block diagram of the on-chip reset circuit is
shown in Figure 13-4.
The PICmicro® devices have a MCLR noise filter in the
MCLR reset path. The filter will detect and ignore small
pulses.
13.3
Reset
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR)
It should be noted that a WDT reset does not drive
MCLR pin low.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on POR, on the MCLR and WDT Reset, on
MCLR reset during SLEEP, and on BOR. The TO and
PD bits are set or cleared differently in different reset
situations as indicated in Table 13-4. These bits are
used in software to determine the nature of the reset.
See Table 13-7 for a full description of reset states of all
registers.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 97
MICROCHIP [ MICROCHIP ]
