PIC16C745/765
4.2.2.6
PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PERIPHERAL INTERRUPT ENABLE 2 REGISTER (PIE2: 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IE
bit0
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
—
—
—
—
—
—
—
bit7
-n
=
Value at POR reset
bit 7-1: Unimplemented: Read as ’0’
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
4.2.2.7
PIR2 REGISTER
This register contains the CCP2 interrupt flag bit. .
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IF
bit0
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
—
—
—
—
—
—
—
bit7
-n
=
Value at POR reset
bit 7-1: Unimplemented: Read as ’0’
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 27
MICROCHIP [ MICROCHIP ]
