PIC16C745/765
FIGURE 5-1: BLOCK DIAGRAM OF RA<3:0>
AND RA5 PINS
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
Q
VDD
P
VDD
WR
Port
5.1
PORTA and TRISA Registers
CK
PORTA is a 6-bit latch.
Data Latch
D
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL input
levels and full CMOS output drivers. All pins have data
direction bits (TRIS registers), which can configure
these pins as output or input.
N
I/O Pin
Q
Q
WR
TRIS
VSS
CK
Analog
Input
Mode
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
TRIS Latch
Schmitt
Trigger
Input
RD TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified, and then written to the port
data latch.
Buffer
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
RD PORT
On the PIC16C745/765, PORTA pins are multiplexed
with analog inputs and analog VREF input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
To A/D Converter
FIGURE 5-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On all resets, pins with analog and digital
VDD
functions are configured as analog inputs.
Data
Bus
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
D
Q
Q
WR
PORT
CK
I/O pin
N
Data Latch
D
Q
EXAMPLE 5-1: INITIALIZING PORTA
(PIC16C745/765)
VSS
WR
TRIS
Schmitt
Trigger
Input
BCF
BCF
CLRF
STATUS, RP1
STATUS, RP0
PORTA
;
;
Q
CK
TRIS Latch
; Initialize PORTA by
; clearing output
; data latches
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
Buffer
BSF
STATUS, RP0
0x06
ADCON1
0xCF
RD TRIS
MOVLW
MOVWF
MOVLW
Q
D
EN
EN
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
TMR0 Clock Input
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 31
MICROCHIP [ MICROCHIP ]
