PIC16F7X
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
Weak
Pull-up
P
Data Latch
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
Data Bus
WR Port
D
Q
I/O
pin(1)
RB0/INT is discussed in detail in Section 12.11.1.
CK
TRIS Latch
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
D
Q
TTL
Input
Buffer
WR TRIS
CK
VDD
RBPU(2)
Weak
P
Pull-up
RD TRIS
RD Port
RB0/INT
Data Latch
Data Bus
WR Port
D
Q
Q
D
I/O
pin(1)
CK
TRIS Latch
EN
D
Q
WR TRIS
RD TRIS
TTL
Input
Buffer
Schmitt Trigger
Buffer
RD Port
CK
ST
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
Latch
Q
Q
D
Four of the PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the inter-
rupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
RD Port
EN
Q1
Set RBIF
D
RD Port
Q3
From other
RB7:RB4 pins
EN
RB7:RB6 in Serial Programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
2002 Microchip Technology Inc.
DS30325B-page 33
MICROCHIP [ MICROCHIP ]
