PIC16F7X
FIGURE 4-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
4.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data Bus
D
Q
Q
VDD
P
WR Port
CK
Additional information on I/O ports may be found in the
PICmicro™
Mid-Range
Reference
Manual,
Data Latch
(DS33023).
I/O pin(1)
N
D
Q
Q
4.1
PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= ‘1’) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISA bit (= ‘0’) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR TRIS
RD TRIS
RD PORT
VSS
Analog
Input
CK
TRIS Latch
Mode
TTL
Input
Buffer
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
FIGURE 4-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data Bus
D
Q
Q
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
WR PORT
CK
I/O pin(1)
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
N
Data Latch
D
Q
VSS
WRTRIS
RD TRIS
Schmitt
Trigger
Input
Q
CK
EXAMPLE 4-1:
INITIALIZING PORTA
TRIS Latch
Buffer
BCF
STATUS, RP0
;
BCF
CLRF
STATUS, RP1
PORTA
; Bank0
; Initialize PORTA by
; clearing output
; data latches
Q
D
BSF
STATUS, RP0
0x06
ADCON1
0xCF
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
MOVLW
MOVWF
MOVLW
EN
EN
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as ’0’.
TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
2002 Microchip Technology Inc.
DS30325B-page 31
MICROCHIP [ MICROCHIP ]
