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PIC16F73-I/SPG 参数 Datasheet PDF下载

PIC16F73-I/SPG图片预览
型号: PIC16F73-I/SPG
PDF下载: 下载PDF文件 查看货源
内容描述: [28 Pin, 7KB Std Flash, 192 RAM, 22 I/O, -40C to +85C, 28-SPDIP, TUBE]
分类和应用: 闪存微控制器
文件页数/大小: 174 页 / 3853 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X  
When interfacing to the program memory block, the  
PMDATH:PMDATA registers form a two-byte word,  
which holds the 14-bit data for reads. The  
PMADRH:PMADR registers form a two-byte word,  
which holds the 13-bit address of the FLASH location  
being accessed. These devices can have up to 8K  
words of program FLASH, with an address range from  
0h to 3FFFh. The unused upper bits in both the  
PMDATH and PMADRH registers are not implemented  
and read as 0s.  
3.0  
READING PROGRAM MEMORY  
The FLASH Program Memory is readable during nor-  
mal operation over the entire VDD range. It is indirectly  
addressed through Special Function Registers (SFR).  
Up to 14-bit numbers can be stored in memory for use  
as calibration parameters, serial numbers, packed 7-bit  
ASCII, etc. Executing a program memory location con-  
taining data that forms an invalid instruction results in a  
NOP.  
There are five SFRs used to read the program and  
memory. These registers are:  
3.1  
PMADR  
PMCON1  
PMDATA  
PMDATH  
PMADR  
The address registers can address up to a maximum of  
8K words of program FLASH.  
When selecting a program address value, the MSByte  
of the address is written to the PMADRH register and  
the LSByte is written to the PMADR register. The upper  
MSbits of PMADRH must always be clear.  
PMADRH  
The program memory allows word reads. Program  
memory access allows for checksum calculation and  
reading calibration tables.  
3.2  
PMCON1 Register  
PMCON1 is the control register for memory accesses.  
The control bit RD initiates read operations. This bit  
cannot be cleared, only set, in software. It is cleared in  
hardware at the completion of the read operation.  
REGISTER 3-1:  
PMCON1 REGISTER (ADDRESS 18Ch)  
R-1  
reserved  
bit 7  
U-0  
U-0  
U-0  
U-x  
U-0  
U-0  
R/S-0  
RD  
bit 0  
bit 7  
Reserved: Read as 1’  
bit 6-1  
bit 0  
Unimplemented: Read as '0'  
RD: Read Control bit  
1= Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared)  
in software.  
0= FLASH read completed  
Legend:  
R = Readable bit  
W = Writable bit  
U = Unimplemented bit, read as 0’  
0= Bit is cleared x = Bit is unknown  
- n = Value at POR reset  
1= Bit is set  
2002 Microchip Technology Inc.  
DS30325B-page 29