PIC16C63A/65B/73B/74B
10.3.2
MASTER MODE
10.3.3
MULTI-MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET, or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I
2
C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (an SSP Interrupt will occur, if
enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 =
1011),
or with the
slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I
2
C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
TABLE 10-3:
Address
REGISTERS ASSOCIATED WITH I
2
C OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
Value on
all other
RESETS
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111
Name
0Bh, 8Bh
0Ch
8Ch
13h
93h
14h
94h
87h
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISC
GIE
PEIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
T0IF
INTF
RBIF
PSPIF
(1)
ADIF
(2)
PSPIE
(1)
ADIE
(2)
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
Synchronous Serial Port Receive Buffer/Transmit register
Synchronous Serial Port (I
2
C mode) Address register
WCOL
SMP
(3)
SSPOV SSPEN
CKE
(3)
D/A
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
UA
BF
PORTC Data Direction register
Legend:
x
= unknown,
u
= unchanged, - = unimplemented locations read as ’0’.
Shaded cells are not used by SSP module in I
2
C mode.
Note 1:
PSPIF and PSPIE are reserved on the PIC16C63A/73B; always maintain these bits clear.
2:
ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear.
3:
Maintain these bits clear in I
2
C mode.
DS30605C-page 64
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
