PIC16C63A/65B/73B/74B
10.3.1.1
Addressing
1.
2.
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated START condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
3.
4.
5.
6.
7.
8.
9.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 10-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address, the first byte
would equal ‘1111
0 A9 A8 0’,
where
A9
and
A8
are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7 - 9 for
slave-transmitter:
TABLE 10-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR
→
SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Status Bits as Data
Transfer is Received
BF
0
1
1
0
Note:
SSPOV
0
Yes
Yes
Yes
0
No
No
Yes, SSPOV is set
1
No
No
Yes
1
No
No
Yes
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
2000 Microchip Technology Inc.
DS30605C-page 61
MICROCHIP [ MICROCHIP TECHNOLOGY ]
