PIC16C63A/65B/73B/74B
FIGURE 10-4:
SS
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
SSPIF
bit0
TABLE 10-1:
Address
0Bh,8Bh
0Ch
8Ch
87h
13h
14h
85h
94h
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
GIE
PSPIF
(1)
PSPIE
(1)
Bit 6
PEIE
ADIF
(2)
ADIE
(2)
Bit 5
T0IE
RCIF
RCIE
Bit 4
INTE
TXIF
TXIE
Bit 3
RBIE
SSPIF
SSPIE
Bit 2
T0IF
Bit 1
INTF
Bit 0
RBIF
Value on:
POR,
BOR
Value on
all other
RESETS
Name
INTCON
PIR1
PIE1
TRISC
SSPBUF
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
SSPM1
SSPM0
0000 0000 0000 0000
--11 1111 --11 1111
UA
BF
0000 0000 0000 0000
PORTC Data Direction register
Synchronous Serial Port Receive Buffer/Transmit register
SSPOV SSPEN
—
CKE
CKP
SSPM3 SSPM2
SSPCON WCOL
TRISA
SSPSTAT
—
SMP
PORTA Data Direction register
D/A
P
S
R/W
Legend:
x
= unknown,
u
= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1:
Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2:
Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 59
MICROCHIP [ MICROCHIP TECHNOLOGY ]
