PIC16F872-I/SS 参数 Datasheet PDF下载

PIC16F872

TABLE 2-1:

Address

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(2)

0000 0000

Bank 2

100h

(3)

101h

102h

(3)

INDF

TMR0

PCL

STATUS

FSR

—

PORTB

—

—

—

PCLATH

INTCON

EEDATA

EEADR

EEDATH

EEADRH

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

—

—

—

—

—

—

—

—

103h

(3)

104h

(3)

105h

106h

107h

108h

109h

10Ah

(1,3)

10Bh

(3)

10Ch

10Dh

10Eh

10Fh

Bank 3

180h

(3)

181h

182h

(3)

183h

(3)

184h

186h

187h

188h

189h

18Ah

(1,3)

(3)

Indirect data memory address pointer

Unimplemented

PORTB Data Latch when written: PORTB pins when read

Unimplemented

Unimplemented

Unimplemented

—

GIE

—

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

xxxx xxxx uuuu uuuu

---0 0000 ---0 0000

0000 000x 0000 000u

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

EEPROM data register

EEPROM address register

—

—

—

—

EEPROM data register high byte

—

EEPROM address register high byte

INDF

OPTION_REG

PCL

STATUS

FSR

—

TRISB

—

—

—

PCLATH

INTCON

EECON1

EECON2

—

—

Addressing this location uses contents of FSR to address data memory (not a physical register)

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

—

—

—

—

—

—

—

—

Indirect data memory address pointer

Unimplemented

PORTB Data Direction Register

Unimplemented

Unimplemented

Unimplemented

—

GIE

EEPGD

—

PEIE

—

—

T0IE

—

Write Buffer for the upper 5 bits of the Program Counter

INTE

—

RBIE

WRERR

T0IF

WREN

INTF

WR

RBIF

RD

185h

1111 1111 1111 1111

---0 0000 ---0 0000

0000 000x 0000 000u

x--- x000 x--- u000

---- ---- ---- ----

0000 0000 0000 0000

0000 0000 0000 0000

18Bh

(3)

18Ch

18Dh

18Eh

18Fh

EEPROM control register2 (not a physical register)

Reserved maintain clear

Reserved maintain clear

Legend:

x

= unknown,

u

= unchanged,

q

= value depends on condition, - = unimplemented read as ’0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1:

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2:

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3:

These registers can be addressed from any bank.

4:

These bits are reserved; always maintain these bits clear.

©

1999 Microchip Technology Inc.

Preliminary

DS30221A-page 11