PIC16F872
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
resets
(2)
Value on:
POR,
BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
80h(3)
81h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
OPTION_REG
PCL
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(3)
83h(3)
STATUS
FSR
PD
Z
DC
C
84h(3)
85h
86h
87h
88h
89h
TRISA
TRISB
TRISC
—
—
—
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
—
—
—
—
—
Unimplemented
8Ah(1,3)
PCLATH
INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
8Bh(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PIE1
(4)
—
—
ADIE
(4)
(4)
—
—
(4)
EEIE
—
SSPIE
BCLIE
—
CCP1IE
TMR2IE
—
TMR1IE r0rr 0000 r0rr 0000
PIE2
—
—
(4)
-r-0 0--r -r-0 0--r
---- --qq ---- --uu
PCON
—
POR
BOR
—
Unimplemented
Unimplemented
—
—
—
—
—
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
R/W
RSEN
UA
SEN
BF
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
PR2
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
SSPADD
SSPSTAT
SMP
CKE
D/A
P
S
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRESL
ADCON1
A/D Result Register Low Byte
ADFM
xxxx xxxx uuuu uuuu
PCFG0 0---0000 0---0000
—
—
—
PCFG3
PCFG2
PCFG1
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
DS30221A-page 10
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
