PIC16CE62X
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
FIGURE 4-9: PIE1 REGISTER (ADDRESS 8CH)
U-0
—
R/W-0
CMIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as '0'
4.2.2.5
PIR1 REGISTER
This register contains the individual flag bit for the com-
parator interrupt.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)
U-0
—
R/W-0
CMIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as '0'
DS40182A-page 18
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
