PIC16CE62X
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets
(core and peripheral). The special function registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
The special function registers are registers used by the
CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS FOR THE PIC16CE62X
Value on all
other
resets(1)
Value on
POR/BOR
Reset
Address Name
Bank 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addressing this location uses contents of FSR to address data memory (not a physical
register)
00h
INDF
xxxx xxxx
xxxx xxxx
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
TMR0
Timer0 Module’s Register
xxxx xxxx
0000 0000
0001 1xxx
uuuu uuuu
0000 0000
000q quuu
PCL
Program Counter's (PC) Least Significant Byte
IRP(2)
RP1(2)
STATUS
FSR
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
xxxx xxxx
---x 0000
xxxx xxxx
—
uuuu uuuu
---u 0000
uuuu uuuu
—
PORTA
—
—
—
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
PORTB
RB7
RB6
RB5
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIR1
—
—
—
—
—
GIE
—
—
—
T0IE
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
-0-- ----
—
---0 0000
0000 000x
-0-- ----
—
PEIE
CMIF
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
0Dh-1Eh Unimplemented
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
Bank 1
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
xxxx xxxx
80h
INDF
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
OPTION
PCL
RBPU
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
—
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 1111
1111 1111
—
STATUS
PD
Z
DC
C
FSR
TRISA
—
—
—
TRISB
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIE1
—
—
—
—
—
GIE
—
—
—
T0IE
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
-0-- ----
—
---0 0000
0000 000x
-0-- ----
—
PEIE
CMIE
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
Unimplemented
PCON
—
—
—
—
—
—
POR
BOR
---- --0x
—
---- --uq
—
8Fh-9Eh Unimplemented
90h
9Fh
EEINTF
VRCON
—
—
—
—
—
—
EESCL
VR2
EESDA
VR1
EEVDD
VR0
uuuu u111
000- 0000
uuuu u111
000- 0000
VREN
VROE
VRR
VR3
Legend: — = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
Note 2: IRP & RPI bits are reserved, always maintain these bits clear.
DS40182A-page 14
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
