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PIC16F873A-I/SP 参数 Datasheet PDF下载

PIC16F873A-I/SP图片预览
型号: PIC16F873A-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
9.3.8  
SLEEP OPERATION  
9.3.10  
BUS MODE COMPATIBILITY  
In Master mode, all module clocks are halted, and the  
transmission/reception will remain in that state until the  
device wakes from SLEEP. After the device returns to  
normal mode, the module will continue to transmit/  
receive data.  
Table 9-1 shows the compatibility between the stan-  
dard SPI modes and the states the CKP and CKE con-  
trol bits.  
TABLE 9-1:  
SPI BUS MODES  
In Slave mode, the SPI transmit/receive shift register  
operates asynchronously to the device. This allows the  
device to be placed in SLEEP mode, and data to be  
shifted into the SPI transmit/receive shift register.  
When all 8-bits have been received, the MSSP inter-  
rupt flag bit will be set and if enabled, will wake the  
device from SLEEP.  
Control Bits State  
Standard SPI Mode  
Terminology  
CKP  
CKE  
0, 0  
0, 1  
1, 0  
1, 1  
0
0
1
1
1
0
1
0
9.3.9  
EFFECTS OF A RESET  
There is also a SMP bit which controls when the data is  
sampled.  
A reset disables the MSSP module and terminates the  
current transfer.  
TABLE 9-2:  
REGISTERS ASSOCIATED WITH SPI OPERATION  
Value on  
POR,  
BOR  
Value on  
all other  
RESETS  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
INTCON  
GIE/GIEH  
PEIE/  
GIEL  
TMR0IE INT0IE  
RBIE  
TMR0IF  
CCP1IF  
INT0IF  
RBIF  
0000 000x 0000 000u  
(1)  
PIR1  
PIE1  
PSPIF  
ADIF  
ADIE  
ADIP  
RCIF  
RCIE  
RCIP  
TXIF  
TXIE  
TXIP  
SSPIF  
SSPIE  
SSPIP  
TMR2IF TMR1IF 0000 0000 0000 0000  
(1)  
PSPIE  
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000  
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000  
1111 1111 1111 1111  
(1)  
IPR1  
PSPIP  
TRISC  
PORTC Data Direction Register  
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register  
xxxx xxxx uuuu uuuu  
SSPCON  
TRISA  
WCOL  
SSPOV SSPEN  
PORTA Data Direction Register  
CKE D/A  
CKP  
SSPM3  
SSPM2  
R/W  
SSPM1  
UA  
SSPM0 0000 0000 0000 0000  
--11 1111 --11 1111  
SSPSTAT  
SMP  
P
S
BF  
0000 0000 0000 0000  
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.  
Shaded cells are not used by the MSSP in SPI mode.  
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices. Always maintain these bits clear.  
2001 Microchip Technology Inc.  
Advance Information  
DS39582A-page 77  
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