PIC16F/LF1946/47
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 23-6, Figure 23-8 and Figure 23-9,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
23.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx line. The master
determines when the slave (Processor 2, Figure 23-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• Fosc/(4 * (SSPxADD + 1))
Figure 23-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 23-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDOx
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDOx
(CKE = 1)
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 241
MICROCHIP [ MICROCHIP ]
