PIC16F/LF1946/47
12.8.2
PORTG FUNCTIONS AND OUTPUT
PRIORITIES
12.8 PORTG Registers
PORTG is
a 8-bit wide, bidirectional port. The
Each PORTG pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
corresponding data direction register is TRISG
(Register 12-25). Setting a TRISG bit (= 1) will make the
corresponding PORTG pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISG bit (= 0) will make the corresponding
PORTG pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-4 shows how to initialize PORTG.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
Reading the PORTG register (Register 12-24) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATG).
RG0
1. CCP3 (CCP)
2. P3A (CCP)
3. SEG42 (LCD)
The TRISG register (Register 12-25) controls the
PORTG pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISG register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RG1
1. AN15 (ADC)
2. CPS15 (CSM)
3. TX2 (EUSART)
4. CK2 (EUSART)
5. C3OUT (Comparator)
6. SEG43 (LCD)
12.8.1
ANSELG REGISTER
The ANSELG register (Register 12-27) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELG bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
RG2
1. AN14 (ADC)
The state of the ANSELG bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
2. CPS14 (CSM)
3. DT2/RX2 (EUSART)
4. C3IN+ (Comparator)
5. SEG44 (LCD)
RG3
Note:
The ANSELG register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
1. AN13 (ADC)
2. CPS13 (CSM)
3. C3IN0- (Comparator)
4. CCP4 (CCP)
5. P3D (CCP)
EXAMPLE 12-7:
INITIALIZING PORTG
6. SEG45 (LCD)
BANKSEL PORTG
;
RG4
CLRF
BANKSEL LATG
CLRF LATG
BANKSEL ANSELG
CLRF ANSELG
BANKSEL TRISG
PORTG
;Init PORTG
;Data Latch
;
;
;digital I/O
;
1. AN12 (ADC)
2. CPS12 (CSM)
3. C3IN1- (Comparator)
4. CCP5 (CCP)
5. P1D (CCP)
MOVLW
MOVWF
B'11110000' ;Set RG<7:4> as inputs
TRISG
;and set RG<3:0> as
;outputs
6. SEG26 (LCD)
RG5
1. VPP/MCLR (Basic)SEG18 (LCD)
DS41414A-page 142
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
