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PIC16C74B-04/P 参数 Datasheet PDF下载

PIC16C74B-04/P图片预览
型号: PIC16C74B-04/P
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS微控制器 [28/40-Pin 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管可编程只读存储器时钟
文件页数/大小: 184 页 / 2122 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C63A/65B/73B/74B  
ered register, i.e., it is a two-deep FIFO. It is possible  
for two bytes of data to be received and transferred to  
the RCREG FIFO and a third byte to begin shifting to  
the RSR register. On the detection of the STOP bit of  
the third byte, if the RCREG register is still full, then  
overrun error bit OERR (RCSTA<1>) will be set. The  
word in the RSR will be lost. The RCREG register can  
be read twice to retrieve the two bytes in the FIFO.  
Overrun bit OERR has to be cleared in software. This  
is done by resetting the receive logic (CREN is cleared  
and then set). If bit OERR is set, transfers from the  
RSR register to the RCREG register are inhibited, and  
no further data will be received; therefore, it is essential  
to clear error bit OERR if it is set. Framing error bit  
FERR (RCSTA<2>) is set if a STOP bit is detected as  
clear. Bit FERR and the 9th receive bit are buffered the  
same way as the receive data. Reading the RCREG  
will load bits RX9D and FERR with new values, there-  
fore, it is essential for the user to read the RCSTA reg-  
ister before reading the RCREG register, in order not to  
lose the old FERR and RX9D information.  
11.2.2  
USART ASYNCHRONOUS  
RECEIVER  
The receiver block diagram is shown in Figure 11-4.  
The data is received on the RC7/RX/DT pin and drives  
the data recovery block. The data recovery block is  
actually a high speed shifter operating at x16 times the  
baud rate, whereas the main receive serial shifter oper-  
ates at the bit rate or at FOSC.  
Once Asynchronous mode is selected, reception is  
enabled by setting bit CREN (RCSTA<4>).  
The heart of the receiver is the receive (serial) shift reg-  
ister (RSR). After sampling the STOP bit, the received  
data in the RSR is transferred to the RCREG register (if  
it is empty). If the transfer is complete, USART Receive  
Flag bit RCIF (PIR1<5>) is set. This interrupt can be  
enabled/disabled by setting/clearing the USART  
Receive Enable bit RCIE (PIE1<5>).  
Flag bit RCIF is a read only bit, which is cleared by the  
hardware. It is cleared when the RCREG register has  
been read and is empty. The RCREG is a double buff-  
FIGURE 11-4:  
USART RECEIVE BLOCK DIAGRAM  
x64 Baud Rate CLK  
FERR  
OERR  
CREN  
FOSC  
SPBRG  
RSR Register  
MSb  
LSb  
÷ 64  
or  
÷ 16  
Baud Rate Generator  
1
0
START  
STOP (8)  
• • •  
7
RC7/RX/DT  
Pin Buffer  
and Control  
Data  
Recovery  
RX9  
RX9D  
SPEN  
RCREG Register  
FIFO  
8
RCIF  
RCIE  
Interrupt  
Data Bus  
DS30605C-page 70  
2000 Microchip Technology Inc.