PIC16C63A/65B/73B/74B
Steps to follow when setting up an Asynchronous
Reception:
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, set interrupt enable bits
RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
FIGURE 11-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the
third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user’s firmware.
TABLE 11-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
1Ah
RCREG USART Receive register
(1)
(2)
8Ch
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
99h
SPBRG Baud Rate Generator register
Legend: u= unchanged, x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 71
MICROCHIP [ MICROCHIP ]
