PIC16C63A/65B/73B/74B
4.2.2.4
PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE(2)
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
R/W-0
R/W-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE(2): A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented; always
maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D implemented; always maintain this bit
clear.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 22
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
