PIC16C63A/65B/73B/74B
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF(4)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
OPTION_REG RBPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP(2) RP1(2)
RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
PCL(4)
STATUS(4)
FSR(4)
TRISA
TRISB
TRISC
TRISD(5)
TRISE(5)
PCLATH(1,4)
INTCON(4)
PIE1
PD
Z
DC
C
—
—
PORTB Data Direction register
PORTC Data Direction register
PORTD Data Direction register
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction bits
Write Buffer for the upper 5 bits of the Program Counter
GIE
PSPIE(5)
—
PEIE
ADIE(6)
—
T0IE
RCIE
—
INTE
TXIE
—
RBIE
SSPIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
PIE2
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
PR2
Timer2 Period register
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
SSPADD
SSPSTAT
—
Synchronous Serial Port (I2C mode) Address register
—
—
D/A
P
S
R/W
UA
BF
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1(6)
—
—
—
—
—
PCFG2
PCFG1
PCFG0 -----000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
DS30605C-page 18
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
