PIC16C62B/72A
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(4)
Bank 0
00h
INDF(1)
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h
Timer0 module’s register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
02h
PCL(1)
Program Counter's (PC) Least Significant Byte
03h
STATUS(1)
FSR(1)
IRP(5)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1(5)
RP0
TO
PD
Z
DC
C
04h
05h
PORTA(6,7)
PORTB(6,7)
PORTC(6,7)
—
—
—
06h
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
07h
08h-09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
—
—
PCLATH(1,2)
INTCON(1)
PIR1
—
GIE
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
PEIE
INTE
—
RBIE
T0IF
INTF
RBIF
ADIF(3)
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
—
Unimplemented
—
—
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H
T1CON
TMR2
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h
Timer2 module’s register
0000 0000 0000 0000
12h
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
14h
WCOL
SSPOV
SSPEN
CKP
SSPM3
CCP1M3
CHS0
SSPM2
SSPM1
15h
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
16h
xxxx xxxx uuuu uuuu
17h
—
—
CCP1X
CHS2
CCP1Y
CHS1
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh
1Eh
1Fh
Unimplemented
—
—
ADRES(3)
ADCON0(3)
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
GO/DONE
—
ADON
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as ’0’,
Shaded locations are unimplemented, read as ’0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 9
MICROCHIP [ MICROCHIP ]
