PIC12F635/PIC16F636/639
REGISTER 7-5:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
VREN
U-0
—
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
VREN: CVREF Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 6
bit 5
Unimplemented: Read as ‘0’
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR<3:0>: CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15)
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
FIGURE 7-10:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
VRR
8R
16-1 Analog
MUX
VREN
15
14
CVREF to
Comparator
Input
2
1
0
(1)
VR<3:0>
VREN
VR<3:0> = 0000
VRR
Note 1: Care should be taken to ensure VREF remains
within the comparator common mode input
range. See Section 15.0 “Electrical Specifica-
tions” for more detail.
DS41232D-page 84
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
