PIC12F635/PIC16F636/639
8.1
PLVD Operation
8.4
Stable Reference Indication
To setup the PLVD for operation, the following steps
must be taken:
When the PLVD module is enabled, the reference volt-
age must be allowed to stabilize before the PLVD will
provide a valid result. Refer to Electrical Section,
PLVD Characteristics for the stabilization time.
• Enable the module by setting the LVDEN bit of the
LVDCON register.
When the HFINTOSC is running, the IRVST bit of the
LVDCON register indicates the stability of the voltage
reference. The voltage reference is stable when the
IRVST bit is set.
• Configure the trip point by setting the LVDL<2:0>
bits of the LVDCON register.
• Wait for the reference voltage to become stable.
Refer to Section 8.4 “Stable Reference
Indication”.
8.5
Operation During Sleep
• Clear the LVDIF bit of the PIRx register.
To wake from Sleep, set the LVDIE bit of the PIEx
register and the PEIE bit of the INTCON register. When
the LVDIE and PEIE bits are set, the device will wake
from Sleep and execute the next instruction. If the GIE
bit is also set, the program will call the Interrupt Service
Routine upon completion of the first instruction after
waking from Sleep.
The LVDIF bit will be set when VDD falls below the
PLVD trip point. The LVDIF bit remains set until cleared
by software. Refer to Figure 8-2.
8.2
Programmable Trip Point
The PLVD trip point is selectable from one of eight
voltage levels. The LVDL bits of the LVDCON register
select the trip point. Refer to Register 8-1 for the
available PLVD trip points.
8.3
Interrupt on Falling VDD
When VDD falls below the PLVD trip point, the falling
edge detector will set the LVDIF bit. See Figure 8-2. An
interrupt will be generated if the following bits are also
set:
• GIE and PEIE bits of the INTCON register
• LVDIE bit of the PIEx register
The LVDIF bit must be cleared by software. An interrupt
can be generated from a simulated PLVD event when
the LVDIF bit is set by software.
DS41232D-page 88
© 2007 Microchip Technology Inc.
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