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PIC12F635-I/SN 参数 Datasheet PDF下载

PIC12F635-I/SN图片预览
型号: PIC12F635-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 8月14日引脚,基于闪存的8位CMOS微控制器采用纳瓦技术 [8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 234 页 / 3856 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F635/PIC16F636/639  
7.7  
Operation During Sleep  
7.8  
Effects of a Reset  
The comparator, if enabled before entering Sleep mode,  
remains active during Sleep. The additional current  
consumed by the comparator is shown separately in the  
Section 15.0 “Electrical Specifications”. If the  
comparator is not used to wake the device, power  
consumption can be minimized while in Sleep mode by  
turning off the comparator. The comparator is turned off  
by selecting mode CM<2:0> = 000or CM<2:0> = 111  
of the CMCON0 register.  
A device Reset forces the CMCON0 and CMCON1  
registers to their Reset states. This forces the Compar-  
ator module to be in the Comparator Reset mode  
(CM<2:0> = 000). Thus, all comparator inputs are  
analog inputs with the comparator disabled to consume  
the smallest current possible.  
A change to the comparator output can wake-up the  
device from Sleep. To enable the comparator to wake  
the device from Sleep, the CxIE bit of the PIE1 register  
and the PEIE bit of the INTCON register must be set.  
The instruction following the Sleep instruction always  
executes following a wake from Sleep. If the GIE bit of  
the INTCON register is also set, the device will then  
execute the Interrupt Service Routine.  
REGISTER 7-1:  
CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC12F635)  
U-0  
R-0  
U-0  
R/W-0  
CINV  
R/W-0  
CIS  
R/W-0  
CM2  
R/W-0  
CM1  
R/W-0  
CM0  
COUT  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared  
x = Bit is unknown  
bit 7  
bit 6  
Unimplemented: Read as ‘0’  
COUT: Comparator Output bit  
When CINV = 0:  
1= VIN+ > VIN-  
0= VIN+ < VIN-  
When CINV = 1:  
1= VIN+ < VIN-  
0= VIN+ > VIN-  
bit 5  
bit 4  
Unimplemented: Read as ‘0’  
CINV: Comparator Output Inversion bit  
1= Output inverted  
0= Output not inverted  
bit 3  
CIS: Comparator Input Switch bit  
When CM<2:0> = 110or 101:  
1= CIN+ connects to VIN-  
0= CIN- connects to VIN-  
When CM<2:0> = 0xxor 100or 111:  
CIS has no effect.  
bit 2-0  
CM<2:0>: Comparator Mode bits (See Figure 7-5)  
000= CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off  
001= CIN pins are configured as analog, COUT pin configured as Comparator output  
010= CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally  
011= CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as  
Comparator output, CVREF is non-inverting input  
100= CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output  
available internally, CVREF is non-inverting input  
101= CIN pins are configured as analog and multiplexed, COUT pin is configured as  
Comparator output, CVREF is non-inverting input  
110= CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O,  
Comparator output available internally, CVREF is non-inverting input  
111= CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.  
© 2007 Microchip Technology Inc.  
DS41232D-page 79  
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