PIC12F635/PIC16F636/639
FIGURE 7-8:
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
Q1
Q3
CIN+
TRT
CxOUT
Set CxIF (level)
CxIF
reset by software
FIGURE 7-9:
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
Q1
Q3
CIN+
TRT
CxOUT
Set CxIF (level)
CxIF
cleared by CMCON0 read
reset by software
Note 1: If a change in the CMCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF of the PIR1
register interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1 μs for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.
DS41232D-page 78
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
