PIC12F635/PIC16F636/639
FIGURE 12-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF Flag
(INTCON<1>)
Interrupt Latency(3)
GIE bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Inst(PC – 1)
Fetched
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3: GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.13 Code Protection
12.14 ID Locations
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP for verification purposes.
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
Note:
The entire data EEPROM and Flash pro-
gram memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
DS41232D-page 146
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
