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PIC12F635-I/SN 参数 Datasheet PDF下载

PIC12F635-I/SN图片预览
型号: PIC12F635-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 8月14日引脚,基于闪存的8位CMOS微控制器采用纳瓦技术 [8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 234 页 / 3856 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F635/PIC16F636/639  
TABLE 13-1: OPCODE FIELD  
13.0 INSTRUCTION SET SUMMARY  
DESCRIPTIONS  
The PIC12F635/PIC16F636/639 instruction set is  
highly orthogonal and is comprised of three basic  
categories:  
Field  
Description  
f
W
b
Register file address (0x00 to 0x7F)  
Working register (accumulator)  
Byte-oriented operations  
Bit-oriented operations  
Bit address within an 8-bit file register  
Literal field, constant data or label  
Literal and control operations  
k
Each PIC16 instruction is a 14-bit word divided into an  
opcode, which specifies the instruction type and one or  
more operands, which further specify the operation of  
the instruction. The formats for each of the categories  
is presented in Figure 13-1, while the various opcode  
fields are summarized in Table 13-1.  
x
Don’t care location (= 0or 1).  
The assembler will generate code with x = 0.  
It is the recommended form of use for  
compatibility with all Microchip software tools.  
d
Destination select; d = 0: store result in W,  
d = 1: store result in file register f.  
Default is d = 1.  
Table 13-2 lists the instructions recognized by the  
MPASMTM assembler.  
PC  
TO  
C
Program Counter  
Time-out bit  
Carry bit  
For byte-oriented instructions, ‘f’ represents a file  
register designator and ‘d’ represents a destination  
designator. The file register designator specifies which  
file register is to be used by the instruction.  
DC  
Z
Digit carry bit  
Zero bit  
The destination designator specifies where the result of  
the operation is to be placed. If ‘d’ is zero, the result is  
placed in the W register. If ‘d’ is one, the result is placed  
in the file register specified in the instruction.  
PD  
Power-down bit  
FIGURE 13-1:  
GENERAL FORMAT FOR  
INSTRUCTIONS  
For bit-oriented instructions, ‘b’ represents a bit field  
designator, which selects the bit affected by the  
operation, while ‘f’ represents the address of the file in  
which the bit is located.  
Byte-oriented file register operations  
13  
8
7
6
0
OPCODE  
d
f (FILE #)  
For literal and control operations, ‘k’ represents an  
d = 0for destination W  
d = 1for destination f  
f = 7-bit file register address  
8-bit or 11-bit constant, or literal value.  
One instruction cycle consists of four oscillator periods;  
for an oscillator frequency of 4 MHz, this gives a  
nominal instruction execution time of 1 μs. All  
instructions are executed within a single instruction  
cycle, unless a conditional test is true, or the program  
counter is changed as a result of an instruction. When  
this occurs, the execution takes two instruction cycles,  
with the second cycle executed as a NOP.  
Bit-oriented file register operations  
13 10 9  
b (BIT #)  
7
6
0
OPCODE  
f (FILE #)  
b = 3-bit bit address  
f = 7-bit file register address  
All instruction examples use the format ‘0xhh’ to  
represent a hexadecimal number, where ‘h’ signifies a  
hexadecimal digit.  
Literal and control operations  
General  
13  
8
7
0
0
OPCODE  
k (literal)  
13.1 Read-Modify-Write Operations  
k = 8-bit immediate value  
Any instruction that specifies a file register as part of  
the instruction performs a Read-Modify-Write (R-M-W)  
operation. The register is read, the data is modified,  
and the result is stored according to either the  
instruction, or the destination designator ‘d’. A read  
operation is performed on a register even if the  
instruction writes to that register.  
CALLand GOTOinstructions only  
13 11 10  
OPCODE  
k = 11-bit immediate value  
k (literal)  
For example, a CLRF PORTA instruction will read  
PORTA, clear all the data bits, then write the result back  
to PORTA. This example would have the unintended  
consequence of clearing the condition that set the RAIF  
flag.  
© 2007 Microchip Technology Inc.  
DS41232D-page 149  
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