PIC12F683
TABLE 2-1:
PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0
Value on
POR, BOD
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h INDF
01h TMR0
02h PCL
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83
Timer0 Module’s Register
xxxx xxxx 39, 83
0000 0000 17, 83
0001 1xxx 11, 83
xxxx xxxx 17, 83
--xx xxxx 31, 83
Program Counter’s (PC) Least Significant Byte
(1)
(1)
03h STATUS
04h FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
05h GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
06h
07h
08h
09h
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 17, 83
0000 0000 13, 83
GIE
EEIF
PEIE
ADIF
T0IE
INTE
—
GPIE
CMIF
T0IF
INTF
GPIF
CCP1IF
OSFIF
TMR2IF
TMR1IF 000- 0000 15, 83
0Dh
—
Unimplemented
—
—
0Eh TMR1L
0Fh TMR1H
10h T1CON
Holding Register for the Least Significant Byte of the 16-bit TMR1
Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx 41, 83
xxxx xxxx 41, 83
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 43, 83
Timer2 Module Register 0000 0000 45, 83
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 45, 83
11h
TMR2
12h T2CON
—
13h CCPR1L Capture/Compare/PWM Register 1 Low Byte
14h CCPR1H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 70, 83
xxxx xxxx 70, 83
15h CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 69, 83
16h
17h
—
—
Unimplemented
Unimplemented
—
—
—
—
18h WDTCON
19h CMCON0
1Ah CMCON1
—
—
—
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 90, 83
COUT
—
CINV
—
CIS
—
CM2
—
CM1
CM0
-0-0 0000 47, 83
T1GSS
CMSYNC ---- --10 50, 83
1Bh
1Ch
1Dh
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
1Fh ADCON0 ADFM VCFG CHS1 CHS0 GO/DONE
Legend:
xxxx xxxx 57,83
—
—
ADON 00-- 0000 58,83
— = unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 9
MICROCHIP [ MICROCHIP ]
