PIC10F200/202/204/206
TABLE 10-2:
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
INSTRUCTION SET SUMMARY
Description
Cycles
12-Bit Opcode
MSb
LSb
Status
Notes
Affected
0001 11df ffff
C, DC, Z
1, 2, 4
Add W and f
1
0001 01df ffff
AND W with f
1
Z
2, 4
0000 011f ffff
Clear f
1
Z
4
0000 0100 0000
Clear W
1
Z
0010 01df ffff
Complement f
1
Z
0000 11df ffff
Decrement f
1
Z
2, 4
(2)
0010 11df ffff
Decrement f, Skip if 0
1
None
2, 4
1
0010 10df ffff
Increment f
Z
2, 4
(2)
1
0011 11df ffff
Increment f, Skip if 0
None
2, 4
1
0001 00df ffff
Inclusive OR W with f
Z
2, 4
1
0010 00df ffff
Move f
Z
2, 4
1
0000 001f ffff
Move W to f
None
1, 4
1
0000 0000 0000
No Operation
None
1
0011 01df ffff
Rotate left f through Carry
C
2, 4
1
0011 00df ffff
Rotate right f through Carry
C
2, 4
1
0000 10df ffff
C, DC, Z
1, 2, 4
Subtract W from f
1
0011 10df ffff
Swap f
None
2, 4
1
0001 10df ffff
Exclusive OR W with f
Z
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
0100 bbbf ffff
None
2, 4
Bit Clear f
1
BCF
f, b
0101 bbbf ffff
None
2, 4
Bit Set f
1
BSF
f, b
(2)
0110 bbbf ffff
None
Bit Test f, Skip if Clear
1
BTFSC
f, b
(2)
1
0111 bbbf ffff
None
f, b
Bit Test f, Skip if Set
BTFSS
LITERAL AND CONTROL OPERATIONS
ANDLW
k
AND literal with W
1
1110 kkkk kkkk
Z
CALL
1
k
Call Subroutine
2
1001 kkkk kkkk
None
CLRWDT
Clear Watchdog Timer
1
0000 0000 0100
TO
,
PD
None
GOTO
k
Unconditional branch
2
101k kkkk kkkk
Z
IORLW
k
Inclusive OR literal with W
1
1101 kkkk kkkk
None
MOVLW
k
Move literal to W
1
1100 kkkk kkkk
None
OPTION
—
Load OPTION register
1
0000 0000 0010
None
RETLW
k
Return, place Literal in W
2
1000 kkkk kkkk
SLEEP
—
Go into Standby mode
1
0000 0000 0011
TO
,
PD
None
3
TRIS
f
Load TRIS register
1
0000 0000 0fff
Z
XORLW
k
Exclusive OR literal to W
1
1111 kkkk kkkk
Note 1:
The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO.
See
2:
When an I/O register is modified as a function of itself (e.g.
MOVF PORTB, 1),
the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3:
The instruction
TRIS f,
where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4:
If this instruction is executed on the TMR0 register (and where applicable, d =
1),
the prescaler will be
cleared (if assigned to TMR0).
DS41239D-page 52
©
2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
