PIC10F200/202/204/206
ADDWF
Syntax:
Operands:
Operation:
Description:
Add W and f
[
label
] ADDWF
0
≤
f
≤
31
d
∈ [0,1]
(W) + (f)
→
(dest)
Add the contents of the W register
and register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
f,d
BCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Clear f
[
label
] BCF
0
≤
f
≤
31
0
≤
b
≤
7
0
→
(f<b>)
None
Bit ‘b’ in register ‘f’ is cleared.
f,b
Status Affected: C, DC, Z
ANDLW
Syntax:
Operands:
Operation:
Description:
AND literal with W
[
label
] ANDLW
0
≤
k
≤
255
(W).AND. (k)
→
(W)
k
BSF
Syntax:
Operands:
Operation:
Status Affected:
Bit Set f
[
label
] BSF
0
≤
f
≤
31
0
≤
b
≤
7
1
→
(f<b>)
None
f,b
Status Affected: Z
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description: Bit ‘b’ in register ‘f’ is set.
ANDWF
Syntax:
Operands:
Operation:
Description:
AND W with f
[
label
] ANDWF
0
≤
f
≤
31
d
∈
[0,1]
(W) .AND. (f)
→
(dest)
The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
f,d
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Clear
[
label
] BTFSC f,b
0
≤
f
≤
31
0
≤
b
≤
7
skip if (f<b>) =
0
None
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a
NOP
is executed instead,
making this a two-cycle instruction.
Status Affected: Z
©
2007 Microchip Technology Inc.
DS41239D-page 53
MICROCHIP [ MICROCHIP TECHNOLOGY ]
