PIC10F200/202/204/206
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Set
[
label
] BTFSS f,b
0
≤
f
≤
31
0
≤
b<7
skip if (f<b>) =
1
None
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a
NOP
is executed instead,
making this a two-cycle instruction.
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Clear W
[
label
] CLRW
None
00h
→
(W);
1
→
Z
Z
The W register is cleared. Zero bit
(Z) is set.
CALL
Syntax:
Operands:
Operation:
Subroutine Call
[
label
] CALL k
0
≤
k
≤
255
(PC) + 1→ Top-of-Stack;
k
→
PC<7:0>;
(STATUS<6:5>)
→
PC<10:9>;
0
→
PC<8>
None
Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL
is a two-cycle instruction.
CLRWDT
Syntax:
Operands:
Operation:
Clear Watchdog Timer
[
label
] CLRWDT
None
00h
→
WDT;
0
→
WDT prescaler (if assigned);
1
→
TO;
1
→
PD
TO, PD
The
CLRWDT
instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
Status Affected:
Description:
Status Affected:
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Clear f
[
label
] CLRF
0
≤
f
≤
31
00h
→
(f);
1
→
Z
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
f
COMF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Complement f
[
label
] COMF
0
≤
f
≤
31
d
∈
[0,1]
(f)
→
(dest)
Z
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
f,d
DS41239D-page 54
©
2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
