PIC10F200/202/204/206
FIGURE 7-2:
PC
(Program
Counter)
Instruction
Fetch
Timer0
Instruction
Executed
T0
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1
PC
MOVWF TMR0
PC + 1
PC + 2
PC + 3
PC + 4
PC+5
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
T0 + 2
NT0
NT0 + 1
NT0 + 2
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
FIGURE 7-3:
PC
(Program
Counter)
Instruction
Fetch
Timer0
Instruction
Executed
T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1
PC
PC + 1
PC + 2
PC + 3
PC + 4
PC + 5
PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
NT0
NT0 + 1
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
TABLE 7-1:
Address
01h
07h
N/A
N/A
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
xxxx xxxx
CWU
PS0
1111 1111
1111 1111
---- 1111
PSA
PS2
PS1
Value on
All Other
Resets
uuuu uuuu
uuuu uuuu
1111 1111
---- 1111
Name
TMR0
CMCON0
OPTION
TRISGPIO
(1)
Timer0 – 8-bit Real-Time Clock/Counter
CMPOUT
GPWU
—
COUTEN
GPPU
—
POL
T0CS
—
CMPT0CS CMPON CNREF CPREF
T0SE
—
I/O Control Register
Legend:
Note 1:
Shaded cells not used by Timer0. – = unimplemented,
x
= unknown,
u
= unchanged.
The TRIS of the T0CKI pin is overridden when T0CS =
1.
7.1
Using Timer0 with an External
Clock (PIC10F204/206)
small RC delay of 2 Tt0H) and low for at least 2 T
OSC
(and a small RC delay of 2 Tt0H). Refer to the electrical
specification of the desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI or the comparator
output to have a period of at least 4 T
OSC
(and a small
RC delay of 4 Tt0H) divided by the prescaler value. The
only requirement on T0CKI or the comparator output
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (T
OSC
) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
7.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
comparator output to be high for at least 2 T
OSC
(and a
DS41239D-page 34
©
2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
