PIC10F200/202/204/206
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
Prescaler Output
(2)
External Clock/Prescaler
Output After Sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
(3)
(1)
T0 + 2
Note 1:
2:
3:
Delay from clock input change to Timer0 increment is 3 T
OSC
to 7 T
OSC
(Duration of Q = T
OSC
). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 T
OSC
max.
External clock if no prescaler selected; prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.
6.2
Prescaler
6.2.1
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see
For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
Note:
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during pro-
gram execution). To avoid an unintended device Reset,
the following instruction sequence (Example 6-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0
→
WDT)
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g.,
CLRF 1, MOVWF 1,
BSF 1,x,
etc.) will clear the prescaler. When assigned
to WDT, a
CLRWDT
instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a Reset, the prescaler contains all ‘0’s.
CLRWDT
;Clear WDT
CLRF
TMR0
;Clear TMR0 & Prescaler
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
CLRWDT
;PS<2:0> are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION
;desired WDT rate
©
2007 Microchip Technology Inc.
DS41239D-page 31
MICROCHIP [ MICROCHIP TECHNOLOGY ]
