PIC10F200/202/204/206
7.0
TIMER0 MODULE AND TMR0
REGISTER (PIC10F204/206)
The second Counter mode uses the output of the com-
parator to increment Timer0. It can be entered in two
different ways. The first way is selected by setting the
T0CS bit (OPTION<5>) and clearing the CMPT0CS bit
(CMCON<4>); (COUTEN [CMCON<6>]) does not
affect this mode of operation. This enables an internal
connection between the comparator and the Timer0.
The second way is selected by setting the T0CS bit
bit
(OPTION<5>),
setting
the
CMPT0CS
(CMCON0<4>) and clearing the COUTEN bit
(CMCON0<6>). This allows the output of the compara-
tor onto the T0CKI pin, while keeping the T0CKI input
active. Therefore, any comparator change on the
COUT pin is fed back into the T0CKI input. The T0SE
bit (OPTION<4>) determines the source edge. Clear-
ing the T0SE bit selects the rising edge. Restrictions on
the external clock input as discussed in
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable.
details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
The Timer0 module has the following features:
•
•
•
•
8-bit timer/counter register, TMR0
Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
- External clock from either the T0CKI pin or
from the output of the comparator
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
There are two types of Counter mode. The first Counter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CS bit (OPTION<5>), setting
the CMPT0CS bit (CMCON0<4>) and setting the
COUTEN bit (CMCON0<6>). In this mode, Timer0 will
increment either on every rising or falling edge of pin
T0CKI. The T0SE bit (OPTION<4>) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discussed in detail in
FIGURE 7-1:
T0CKI
Pin
TIMER0 BLOCK DIAGRAM (PIC10F204/206
)
Data Bus
F
OSC
/4
0
1
1
T0SE
(1)
CMPT0CS
(3)
PS
OUT
Sync with
Internal
Clocks
8
TMR0 Reg
Internal
Comparator
Output
1
0
Programmable
Prescaler
(2)
3
T0CS
(1)
PS2, PS1, PS0
(1)
0
PS
OUT
(2 T
CY
delay) Sync
PSA
(1)
Note 1:
2:
3:
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
The prescaler is shared with the Watchdog Timer (Figure 7-5).
Bit CMPT0CS is located in the CMCON0 register, CMCON0<4>.
©
2007 Microchip Technology Inc.
DS41239D-page 33
MICROCHIP [ MICROCHIP TECHNOLOGY ]
