PIC10F200/202/204/206
6.0
TIMER0 MODULE AND TMR0
REGISTER (PIC10F200/202)
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge. Restric-
tions on the external clock input are discussed in detail
in
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, 1:256
are selectable.
details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
The Timer0 module has the following features:
•
•
•
•
8-bit timer/counter register, TMR0
Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
GP2/T0CKI
Pin
TIMER0 BLOCK DIAGRAM
Data Bus
F
OSC
/4
0
1
1
Programmable
Prescaler
(2)
3
T0CS
(1)
PS
OUT
Sync with
Internal
Clocks
8
TMR0 Reg
0
T0SE
(1)
PS
OUT
(2 T
CY
delay) Sync
PS2, PS1, PS0
(1)
PSA
(1)
Note 1:
2:
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
The prescaler is shared with the Watchdog Timer (Figure 6-5).
FIGURE 6-2:
PC
(Program
Counter)
Instruction
Fetch
Timer0
Instruction
Executed
T0
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1
PC
MOVWF TMR0
PC + 1
PC + 2
PC + 3
PC + 4
PC + 5
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
T0 + 2
NT0
NT0 + 1
NT0 + 2
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
©
2007 Microchip Technology Inc.
DS41239D-page 29
MICROCHIP [ MICROCHIP TECHNOLOGY ]
