MCP2515
reading and writing of data. Some specific control and
status registers allow individual bit modification using
the SPI Bit Modify command. The registers that allow
this command are shown as shaded locations in
Table 11-1. A summary of the MCP2515 control
registers is shown in Table 11-2.
11.0 REGISTER MAP
The register map for the MCP2515 is shown in
Table 11-1. Address locations for each register are
determined by using the column (higher-order 4 bits)
and row (lower-order 4 bits) values. The registers
have been arranged to optimize the sequential
TABLE 11-1: CAN CONTROLLER REGISTER MAP
Lower
Address
Bits
Higher-Order Address Bits
0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Note:
RXF0SIDH
RXF0SIDL
RXF0EID8
RXF0EID0
RXF1SIDH
RXF1SIDL
RXF1EID8
RXF1EID0
RXF2SIDH
RXF2SIDL
RXF2EID8
RXF2EID0
BFPCTRL
TXRTSCTRL
CANSTAT
CANCTRL
RXF3SIDH RXM0SIDH
TXB0CTRL
TXB0SIDH
TXB0SIDL
TXB0EID8
TXB0EID0
TXB0DLC
TXB0D0
TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL
TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH
RXF3SIDL
RXF3EID8
RXF3EID0
RXM0SIDL
RXM0EID8
RXM0EID0
TXB1SIDL
TXB1EID8
TXB1EID0
TXB1DLC
TXB1D0
TXB1D1
TXB1D2
TXB1D3
TXB1D4
TXB1D5
TXB1D6
TXB1D7
CANSTAT
CANCTRL
TXB2SIDL
TXB2EID8
TXB2EID0
TXB2DLC
TXB2D0
TXB2D1
TXB2D2
TXB2D3
TXB2D4
TXB2D5
TXB2D6
TXB2D7
CANSTAT
CANCTRL
RXB0SIDL RXB1SIDL
RXB0EID8 RXB1EID8
RXB0EID0 RXB1EID0
RXF4SIDH RXM1SIDH
RXF4SIDL
RXF4EID8
RXF4EID0
RXF5SIDH
RXF5SIDL
RXF5EID8
RXF5EID0
TEC
RXM1SIDL
RXM1EID8
RXM1EID0
CNF3
RXB0DLC
RXB0D0
RXB0D1
RXB0D2
RXB0D3
RXB0D4
RXB0D5
RXB0D6
RXB0D7
CANSTAT
CANCTRL
RXB1DLC
RXB1D0
RXB1D1
RXB1D2
RXB1D3
RXB1D4
RXB1D5
RXB1D6
RXB1D7
CANSTAT
CANCTRL
TXB0D1
TXB0D2
CNF2
TXB0D3
CNF1
TXB0D4
CANINTE
CANINTF
EFLG
TXB0D5
TXB0D6
REC
TXB0D7
CANSTAT
CANCTRL
CANSTAT
CANCTRL
CANSTAT
CANCTRL
Shaded register locations indicate that these allow the user to manipulate individual bits using the Bit Modify command.
TABLE 11-2: CONTROL REGISTER SUMMARY
Register
Name
Address
(Hex)
POR/RST
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BFPCTRL
TXRTSCTRL
CANSTAT
CANCTRL
TEC
0C
0D
xE
xF
1C
1D
28
29
2A
2B
2C
2D
30
40
50
60
70
—
—
—
—
B1BFS
B2RTS
B0BFS
B1RTS
—
B1BFE
B0RTS
ICOD2
OSM
B0BFE
B1BFM
B0BFM --00 0000
B2RTSM B1RTSM B0RTSM --xx x000
ICOD1 ICOD0 100- 000-
OPMOD2 OPMOD1 OPMOD0
REQOP2 REQOP1 REQOP0
—
ABAT
CLKEN CLKPRE1 CLKPRE0 1110 0111
Transmit Error Counter (TEC)
Receive Error Counter (REC)
0000 0000
0000 0000
REC
CNF3
SOF
BTLMODE
SJW1
WAKFIL
SAM
—
—
—
PHSEG22 PHSEG21 PHSEG20 00-- -000
CNF2
PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 0000 0000
CNF1
SJW0
BRP5
ERRIE
ERRIF
TXBO
MLOA
MLOA
MLOA
RXM0
RXM0
BRP4
TX2IE
TX2IF
TXEP
TXERR
TXERR
TXERR
—
BRP3
TX1IE
BRP2
TX0IE
TX0IF
TXWAR
—
BRP1
RX1IE
RX1IF
BRP0
RX0IE
RX0IF
0000 0000
0000 0000
0000 0000
CANINTE
CANINTF
EFLG
MERRE
MERRF
WAKIE
WAKIF
TX1IF
RX1OVR RX0OVR
RXEP
RXWAR EWARN 0000 0000
TXB0CTRL
TXB1CTRL
TXB2CTRL
RXB0CTRL
RXB1CTRL
—
—
—
—
—
ABTF
ABTF
ABTF
RXM1
RSM1
TXREQ
TXREQ
TXREQ
RXRTR
RXRTR
TXP1
TXP1
TXP0
TXP0
TXP0
-000 0-00
-000 0-00
-000 0-00
—
—
TXP1
BUKT
FILHIT2
BUKT
FILHIT1
FILHIT0 -00- 0000
FILHIT0 -00- 0000
—
© 2005 Microchip Technology Inc.
Preliminary
DS21801D-page 61
MICROCHIP [ MICROCHIP ]
