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MCP2515-I/ST 参数 Datasheet PDF下载

MCP2515-I/ST图片预览
型号: MCP2515-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 独立CAN控制器,SPI ™接口 [Stand-Alone CAN Controller With SPI⑩ Interface]
分类和应用: 控制器
文件页数/大小: 84 页 / 993 K
品牌: MICROCHIP [ MICROCHIP ]
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MCP2515  
7.6.2  
RECEIVER WARNING  
7.6.6  
BUS-OFF  
The REC has reached the MCU warning limit of 96.  
The TEC has exceeded 255 and the device has gone  
to bus-off state.  
7.6.3  
TRANSMITTER WARNING  
7.7  
Interrupt Acknowledge  
The TEC has reached the MCU warning limit of 96.  
Interrupts are directly associated with one or more sta-  
tus flags in the CANINTF register. Interrupts are pend-  
ing as long as one of the flags is set. Once an interrupt  
flag is set by the device, the flag can not be reset by the  
MCU until the interrupt condition is removed.  
7.6.4  
RECEIVER ERROR-PASSIVE  
The REC has exceeded the error-passive limit of 127  
and the device has gone to error-passive state.  
7.6.5  
TRANSMITTER ERROR-PASSIVE  
The TEC has exceeded the error- passive limit of 127  
and the device has gone to error- passive state.  
REGISTER 7-1:  
CANINTE – INTERRUPT ENABLE  
(ADDRESS: 2Bh)  
R/W-0  
R/W-0  
R/W-0  
ERRIE  
R/W-0  
TX2IE  
R/W-0  
TX1IE  
R/W-0  
TX0IE  
R/W-0  
RX1IE  
R/W-0  
RX0IE  
MERRE  
WAKIE  
bit 7  
bit 0  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
MERRE: Message Error Interrupt Enable bit  
1= Interrupt on error during message reception or transmission  
0= Disabled  
WAKIE: Wakeup Interrupt Enable bit  
1= Interrupt on CAN bus activity  
0= Disabled  
ERRIE: Error Interrupt Enable bit (multiple sources in EFLG register)  
1 = Interrupt on EFLG error condition change  
0= Disabled  
TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit  
1= Interrupt on TXB2 becoming empty  
0= Disabled  
TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit  
1= Interrupt on TXB1 becoming empty  
0= Disabled  
TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit  
1= Interrupt on TXB0 becoming empty  
0= Disabled  
RX1IE: Receive Buffer 1 Full Interrupt Enable bit  
1= Interrupt when message received in RXB1  
0= Disabled  
RX0IE: Receive Buffer 0 Full Interrupt Enable bit  
1= Interrupt when message received in RXB0  
0= Disabled  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
U = Unimplemented bit, read as ‘0’  
0’ = Bit is cleared x = Bit is unknown  
1’ = Bit is set  
DS21801D-page 50  
Preliminary  
© 2005 Microchip Technology Inc.  
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