MCP1727
5.3.1.2
Junction Temperature Estimate
5.4
CDELAY Calculations (typical)
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
ΔT
ΔV
-------
C = I •
Where:
C
=
=
C
DELAY Capacitor
TJ = TJRISE + TA(MAX)
TJ = 63.14°C + 60.0°C
TJ = 123.14°C
I
CDELAY charging current,
140 nA typical.
ΔT
ΔV
=
=
time delay
As you can see from the result, this application will be
operating very near the maximum operating junction
temperature of 125°C. The PCB layout for this
application is very important as it has a significant
impact on the junction-to-ambient thermal resistance
(RθJA) of the 3x3 DFN package, which is very important
in this application.
CDELAY threshold voltage,
0.42V typical
C = I •
= --------------------------------- = 333.3×10–09 • ΔT
0.42V
ΔT
-------
(140nA • ΔT)
ΔV
For a delay of 300 ms:
C = 333.3E-09 * .300
C = 100E-09uF (0.1 μF)
5.3.1.3
Maximum Package Power
Dissipation at 60°C Ambient
Temperature
3x3DFN (41° C/W RθJA):
P
D(MAX) = (125°C – 60°C) / 41° C/W
D(MAX) = 1.585W
P
SOIC8 (150°C/Watt RθJA):
P
D(MAX) = (125°C – 60°C)/ 150° C/W
D(MAX) = 0.433W
P
From this table, you can see the difference in maximum
allowable power dissipation between the 3x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heatsink,
providing more area to distribute the heat generated by
the LDO.
DS21999B-page 22
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
