KSZ8041NL/RNL
3.13 Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count MII. It provides a common interface between
physical layer and MAC layer devices, and has the following key characteristics:
• Supports 10 Mbps and 100 Mbps data rates
• Uses a 50-MHz reference clock
• Provides independent 2-bit wide (di-bit) transmit and receive data paths
• Contains two distinct groups of signals: one for transmission and the other for reception
The KSZ8041NL is configured in RMII mode after it is powered up or reset with the following:
• A 500MHz reference clock connected to REFCLK (pin 9)
• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’
The KSZ8041RNL is configured in RMII mode and outputs the 50-MHz RMII reference clock to the MAC on REF_CLK
(pin 19) after it is powered up or reset with the following:
• A 25-MHz crystal connected to XI (pin 9) and XO (pin 8), or a 25-MHz reference clock connected to XI (pin 9)
• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’
In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.
3.14 RMII Signal Definition
Table 3-3 and Table 3-4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII specification for
detailed information.
TABLE 3-3:
RMII SIGNAL DESCRIPTION – KSZ8041NL
Direction (with
Direction (with
RMII Signal
Name
respect to PHY,
respect to MAC)
KSZ8041NL signal)
Description
Synchronous 50-MHz clock reference for receive,
transmit, and control interface
REF_CLK
Input
Input or Output
TX_EN
TXD[1:0]
CRS_DV
RXD[1:0]
Input
Input
Output
Output
Input
Transmit Enable
Transmit Data [1:0]
Output
Output
Carrier Sense/Receive Data Valid
Receive Data [1:0]
Input
Input, or (not
required)
RX_ER
Output
Receive Error
TABLE 3-4:
RMII SIGNAL DESCRIPTION – KSZ8041RNL
Direction (with
RMII Signal
Name
respect to PHY,
KSZ8041RNL
signal)
Direction (with
respect to MAC)
Description
Synchronous 50-MHz clock reference for receive,
transmit, and control interface
REF_CLK
Output
Input
TX_EN
TXD[1:0]
CRS_DV
RXD[1:0]
Input
Input
Output
Output
Input
Transmit Enable
Transmit Data [1:0]
Output
Output
Carrier Sense/Receive Data Valid
Receive Data [1:0]
Input
Input, or (not
required)
RX_ER
Output
Receive Error
3.14.1
REFERENCE CLOCK (REF_CLK)
REF_CLK is a continuous 50-MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0],
and RX_ER.
DS00002245B-page 22
2017 Microchip Technology Inc.
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