ENC28J60
registers in the current bank. If the 5-bit address is an
ETH register, then data in the selected register will
immediately start shifting out MSb first on the SO pin.
Figure 4-3 shows the read sequence for these
registers.
4.2.1
READ CONTROL REGISTER
COMMAND
The Read Control Register (RCR) command allows the
host controller to read any of the ETH, MAC and MII
registers in any order. The contents of the PHY regis-
ters are read via a special MII register interface (see
Section 3.3.1 “Reading PHY Registers” for more
information).
If the address specifies one of the MAC or MII registers,
a dummy byte will first be shifted out the SO pin. After
the dummy byte, the data will be shifted out MSb first
on the SO pin. The RCR operation is terminated by
raising the CS pin. Figure 4-4 shows the read
sequence for MAC and MII registers.
The RCR command is started by pulling the CS pin low.
The RCR opcode is then sent to the ENC28J60,
followed by a 5-bit register address (A4 through A0).
The 5-bit address identifies any of the 32 control
FIGURE 4-3:
READ CONTROL REGISTER COMMAND SEQUENCE (ETH REGISTERS)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Opcode
Address
2
0
0
0
4
3
1
0
SI
Data Out
High-Impedance State
7
6
5
4
3
2
1
0
SO
FIGURE 4-4:
READ CONTROL REGISTER COMMAND SEQUENCE
(MAC AND MII REGISTERS)
CS
0
1
2
3
4
5
6
7
0
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Opcode
Address
0
0
0
4
3
2
1
SI
Dummy Byte
Data Byte Out
High-Impedance State
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 27
MICROCHIP [ MICROCHIP ]
