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ENC28J60-I/SO 参数 Datasheet PDF下载

ENC28J60-I/SO图片预览
型号: ENC28J60-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 独立以太网控制器,SPI接口 [Stand-Alone Ethernet Controller with SPI Interface]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路光电二极管数据传输PC局域网以太网时钟
文件页数/大小: 96 页 / 1466 K
品牌: MICROCHIP [ MICROCHIP ]
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ENC28J60  
any of the ETH registers in the current bank. After the  
BFS command and address are sent, the data byte  
containing the bit field set information should be sent,  
MSb first. The supplied data will be logically ORed to  
the content of the addressed register on the rising  
edge of the SCK line for the D0 bit.  
4.2.4  
WRITE BUFFER MEMORY  
COMMAND  
The Write Buffer Memory (WBM) command allows the  
host controller to write bytes to the integrated 8-Kbyte  
transmit and receive buffer memory.  
If the AUTOINC bit in the ECON2 register is set, after  
the last bit of each byte is written, the EWRPT Pointer  
will automatically be incremented to point to the next  
sequential address (current address + 1). If address  
1FFFh is written with AUTOINC set, the Write Pointer  
will increment to 0000h.  
If the CS line is brought high before eight bits are  
loaded, the operation will be aborted for that data  
byte. The BFS operation is terminated by raising the  
CS pin.  
4.2.6  
BIT FIELD CLEAR COMMAND  
The WBM command is started by lowering the CS pin.  
The WBM opcode should then be sent to the  
ENC28J60, followed by the 5-bit constant 1Ah. After  
the WBM command and constant are sent, the data to  
be stored in the memory pointed to by EWRPT should  
be shifted out MSb first to the ENC28J60. After 8 data  
bits are received, the Write Pointer will automatically  
increment if AUTOINC is set. The host controller can  
continue to provide clocks on the SCK pin and send  
data on the SI pin, without raising CS, to keep writing to  
the memory. In this manner, with AUTOINC enabled, it  
is possible to continuously write sequential bytes to the  
buffer memory without any extra SPI command  
overhead.  
The Bit Field Clear (BFC) command is used to clear up  
to 8 bits in any of the ETH Control registers. Note that  
this command cannot be used on the MAC registers,  
MII registers, PHY registers or buffer memory. The BFC  
command uses the provided data byte to perform a bit-  
wise NOTAND operation on the addressed register  
contents. As an example, if a register had the contents  
of F1h and the BFC command was executed with an  
operand of 17h, then the register would be changed to  
have the contents of E0h.  
The BFC command is started by lowering the CS pin.  
The BFC opcode should then be sent, followed by a  
5-bit address (A4 through A0). The 5-bit address  
identifies any of the ETH registers in the current bank.  
After the BFC command and address are sent, a data  
byte containing the bit field clear information should  
be sent, MSb first. The supplied data will be logically  
inverted and subsequently ANDed to the contents of  
the addressed register on the rising edge of the SCK  
line for the D0 bit.  
The WBM command is terminated by bringing up the  
CS pin. Refer to Figure 4-6 for a detailed illustration of  
the write sequence.  
4.2.5  
BIT FIELD SET COMMAND  
The Bit Field Set (BFS) command is used to set up to  
8 bits in any of the ETH Control registers. Note that this  
command cannot be used on the MAC registers, MII  
registers, PHY registers or buffer memory. The BFS com-  
mand uses the provided data byte to perform a bit-wise  
OR operation on the addressed register contents.  
The BFC operation is terminated by bringing the CS  
pin high. If CS is brought high before eight bits are  
loaded, the operation will be aborted for that data  
byte.  
The BFS command is started by pulling the CS pin low.  
The BFS opcode is then sent, followed by a 5-bit  
address (A4 through A0). The 5-bit address identifies  
FIGURE 4-6:  
WRITE BUFFER MEMORY COMMAND SEQUENCE  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
SCK  
Opcode  
Address  
Data Byte 0  
Data Byte 1  
7
6
5
4
3
2
1
0
0
1
1
1
1
0
1
0
7
6
5
4
3
2
1
D0  
SI  
High-Impedance State  
SO  
© 2006 Microchip Technology Inc.  
Preliminary  
DS39662B-page 29