ENC28J60
REGISTER 3-5:
PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1
U-0
—
U-0
—
U-0
—
R-1
R-1
U-0
—
U-0
—
U-0
—
PFDPX
PHDPX
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/LL-0
R/LH-0
U-0
—
LLSTAT
JBSTAT
bit 7
Legend:
‘1’ = Bit is set
R = Read-only bit
-n = Value at POR
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
LL = Bit latches low LH = Bit latches high
R/L = Read-only latch bit
bit 15-13
bit 12
Unimplemented: Read as ‘0’
PFDPX: PHY Full-Duplex Capable bit
1= PHY is capable of operating at 10 Mbps in Full-Duplex mode (this bit is always set)
PHDPX: PHY Half-Duplex Capable bit
bit 11
1= PHY is capable of operating at 10 Mbps in Half-Duplex mode (this bit is always set)
Unimplemented: Read as ‘0’
bit 10-3
bit 2
LLSTAT: PHY Latching Link Status bit
1= Link is up and has been up continously since PHSTAT1 was last read
0= Link is down or was down for a period since PHSTAT1 was last read
bit 1
bit 0
JBSTAT: PHY Latching Jabber Status bit
1= PHY has detected a transmission meeting the jabber criteria since PHSTAT1 was last read
0= PHY has not detected any jabbering transmissions since PHSTAT1 was last read
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 23
MICROCHIP [ MICROCHIP ]
