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DSPIC33FJ128GP306 参数 Datasheet PDF下载

DSPIC33FJ128GP306图片预览
型号: DSPIC33FJ128GP306
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存编程规范 [Flash Programming Specification]
分类和应用: 闪存
文件页数/大小: 80 页 / 943 K
品牌: MICROCHIP [ MICROCHIP ]
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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION  
5.10 Verify Code Memory and  
Configuration Word  
5.11 Reading the Application ID Word  
The Application ID Word is stored at address 0x8007F0  
in executive code memory. To read this memory  
location, you must use the SIX control code to move  
this program memory location to the VISI register.  
Then, the REGOUT control code must be used to clock  
the contents of the VISI register out of the device. The  
corresponding control and instruction codes that must  
be serially transmitted to the device to perform this  
operation are shown in Table 5-11.  
The verify step involves reading back the code memory  
space and comparing it against the copy held in the  
programmer’s buffer. The Configuration registers are  
verified with the rest of the code.  
The verify process is shown in the flowchart in  
Figure 5-8. Memory reads occur a single byte at a time,  
so two bytes must be read to compare against the word  
in the programmer’s buffer. Refer to Section 5.8  
“Reading Code Memory” for implementation details  
of reading code memory.  
After the programmer has clocked out the Application  
ID Word, it must be inspected. If the application ID has  
the value 0xBB, the programming executive is resident  
in memory and the device can be programmed using  
the mechanism described in Section 3.0 “Device  
Programming – Enhanced ICSP”. However, if the  
application ID has any other value, the programming  
executive is not resident in memory; it must be loaded  
to memory before the device can be programmed. The  
procedure for loading the programming executive to  
memory is described in Section 6.0 “Programming  
the Programming Executive to Memory”.  
Note:  
Because the Configuration registers  
include the device code protection bit,  
code memory should be verified immedi-  
ately after writing if code protection is  
enabled. This is because the device will  
not be readable or verifiable if a device  
Reset occurs after the code-protect bit in  
the FGS Configuration register has been  
cleared.  
FIGURE 5-8:  
VERIFY CODE  
MEMORY FLOW  
5.12 Exiting ICSP Mode  
Exiting Program/Verify mode is done by removing VIH  
from MCLR, as shown in Figure 5-9. The only require-  
ment for exit is that an interval P16 should elapse  
between the last clock and program signals on PGC  
and PGD before removing VIH.  
Start  
Set TBLPTR = 0  
FIGURE 5-9:  
EXITING ICSP™ MODE  
P16  
P17  
VIH  
Read Low Byte  
MCLR  
with Post-Increment  
VDD  
Read High Byte  
with Post-Increment  
VIH  
PGD  
PGC  
Does  
Word = Expect  
Data?  
Failure,  
Report  
Error  
No  
PGD = Input  
Yes  
All  
No  
code memory  
verified?  
Yes  
Done  
DS70152D-page 66  
Preliminary  
© 2007 Microchip Technology Inc.  
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