dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-6:
DEFAULT CONFIGURATION
REGISTER VALUES FOR
dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 AND
PIC24HJ12GP201/202
5.7
Writing Configuration Memory
The 8-bit Configuration registers are programmable, one
register at a time. The default programming values rec-
ommended for the Configuration registers are shown in
Table 5-6 and Table 5-7. The recommended default
FOSCSEL value is 0x07, which selects the FRC clock
oscillator setting.
Address
Name
Default Value
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
FBS
FSS
0xCF
0xFF
0x07
0xA7
0xE7
0xDF
0xF7
0xE3
0xFF
0xFF
0xFF
0xFF
The FBS, FSS and FGS Configuration registers are
special since they enable code protection for the
device. For security purposes, once any bit in these
registers is programmed to ‘0’ (to enable code protec-
tion), it can only be set back to ‘1’ by performing a Bulk
Erase as described in Section 5.5 “Erasing Program
Memory”. Programming any of these bits from a ‘0’ to
‘1’ is not possible, but they may be programmed from a
‘1’ to a ‘0’ to enable code protection.
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
Table 5-8 shows the ICSP programming details for clear-
ing the Configuration registers. In Step 1, the Reset vec-
tor is exited. In Step 2, the write pointer (W7) is loaded
with 0x0000, which is the original destination address (in
TBLPAG, 0xF8 of program memory). In Step 3, the
NVMCON is set to program one Configuration register.
In Step 4, the TBLPAG register is initialized to 0xF8 for
writing to the Configuration registers. In Step 5, the value
to write to each Configuration register is loaded to W0.
In Step 6, the Configuration register data is written to the
write latch using the TBLWTLinstruction. In Steps 7 and
8, the programming cycle is initiated. In Step 9, the inter-
nal PC is set to 0x200 as a safety measure to prevent the
PC from incrementing into unimplemented memory.
Lastly, Steps 4-9 are repeated until all twelve
Configuration registers are written.
FUID0
FUID1
FUID2
FUID3
TABLE 5-7:
DEFAULT CONFIGURATION
REGISTER VALUES FOR ALL
OTHER DEVICES
Address
Name
Default Value
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
FBS
FSS
0xCF
0xCF
0x07
0xA7
0xC7
0xDF
0xE7
0xE3
0xFF
0xFF
0xFF
0xFF
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FUID0
FUID1
FUID2
FUID3
DS70152D-page 62
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
