dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
Bit Field
WDTPOST
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
Description
FWDT
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
.
.
.
0001= 1:2
0000= 1:1
PWMPIN
FPOR
Motor Control PWM Module Pin mode
1= PWM module pins controlled by PORT register at device Reset
(tri-stated)
0= PWM module pins controlled by PWM module at device Reset
(configured as output pins)
HPOL
LPOL
FPOR
FPOR
FPOR
Motor Control PWM High-side Polarity bit
1= PWM module high-side output pins have active-high output polarity
0= PWM module high-side output pins have active-low output polarity
Motor Control PWM Low-side Polarity bit
1= PWM module low-side output pins have active-high output polarity
0= PWM module low-side output pins have active-low output polarity
ALTI2C
Alternate I2C™ pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/SACL1 pins
[Note: This bit is only present in the dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]
FPWRT<2:0>
FPOR
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT Disabled
BKBUG
COE
FICD
FICD
FICD
FICD
Background Debug Enable bit
1= Device will reset in User mode
0= Device will reset in Debug mode
Debugger/Emulator Enable bit
1= Device will reset in Operational mode
0= Device will reset in Clip-On Emulation mode
JTAGEN
ICS<1:0>
JTAG Enable bit
1= JTAG enabled
0= JTAG disabled
ICD Communication Channel Select bits
11= Communicate on PGC1/EMUC1 and PGD1/EMUD1
10= Communicate on PGC2/EMUC2 and PGD2/EMUD2
01= Communicate on PGC3/EMUC3 and PGD3/EMUD3
00= Reserved, do not use
—
All
Unimplemented (read as ‘0’, write as ‘0’)
DS70152D-page 44
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
